Successive approximation converters using switched capacitor arrays are well known.
An example of an idealized differential input successive approximation switched capacitor analog to digital converter is shown in FIG. 1. This converter receives a differential signal on its signal inputs Vinp and Vinn, and fixed inputs Vref, and GND. The Vref input and the GND input define an allowable operating range of the converter such that −(Vref-GND)≦(Vinp-Vinn)≦(Vref-GND). The converter comprises two switched capacitor arrays, designated DAC-P and DAC-N (but which may also be referred to as P array and N array herein) which connect to the positive input and negative input, respectively, of a comparator 12. The capacitor arrays DAC-P and DAC-N are mirror images of one another and, for convenience, only the array DAC-P will be described in detail.
The array DAC-P comprises a plurality of binary weighted capacitors C1P to C6P plus C6T whose total capacitance sums to a value C. In this example capacitor C1P represents the most significant bit and capacitor C6P represents the least significant bit of the array. Capacitor C1P has a value of C/2. Consequently C2P has a value of C/4, capacitor C3P has a value of C/8, capacitor C4P has a value of C/16, capacitor C5P has a value of C/32 and capacitor C6P has a value of C/64. In order to ensure that the array sums to its correct value of C, then a further terminating capacitor C6T, having a value corresponding to the value of the least significant bit is included.
Each of the capacitors have first and second plates which, in a commonly used nomenclature are referred to as “top” and “bottom” plates. The top plates of capacitors C1P to C6T are connected to a common rail designated TOP-P which is connected to the positive input of the comparator 12. The bottom plates of capacitor C1P to C6P are connected to respective switches S1P to S6P. The switches are fabricated from transistors. The switch S1P is a three position switch such that the bottom plate of capacitor C1P can either be connected to a positive signal input Vinp, to the positive reference voltage Vref or to a negative reference voltage, e.g. ground. Switches S2P to S6P are two position switches such that the bottom plate of the respective capacitor can either be switched to ground or to Vref. Capacitor C6T (which is a repeat of the least significant bit capacitor) is not associated with a switch and its bottom plate is permanently connected to the negative reference voltage, e.g. the ground rail.
The negative capacitor array SAR-N is identical to that in SAR-P with the exceptions that all capacitors and switches are designated with the subscript N, switch S1N can now connect to a negative signal input Vinn, and that the top plates of capacitors C1N to C6N connect to a common rail designated TOP-N that connects to the negative input of the comparator 12.
Sample switches SSP and SSN are provided to connect the common node TOP-P and the common node TOP-N to a bias voltage, Vbias, during sampling. Vbias can be freely chosen by the circuit designer although in practice it is generally constrained to lie within the voltage range −Vref<Vbias<+Vref. A convenient choice for Vbias is ground because this avoids the need to create a voltage generator solely for the purpose of creating the Vbias voltage. Vbias acts as a reference voltage during sampling of the differential input signal by the converter.
With reference to FIG. 2, it can be seen that each of the switches are implemented as pairs of transistors. For each capacitor its associated switch, such as switch S2P comprises a first transistor 22, which for convenience can be regarded as a high side transistor, which connects it to Vref and a second transistor 24, which for convenience can be regarded as a low side transistor, which connects it to ground. In this example Vref represents the first reference voltage and ground represents the second reference voltage. In use, it is generally considered to be undesirable for the first and second switches, that is the high side and low side switches, to be simultaneously conducting as this provides a short circuit between the first and second reference voltages which either results in unnecessary dissipation within the device and perturbs the reference voltages thereby leading to inaccuracies in the converted result. In order to avoid the high side and low side switches being conducting at the same time, non-overlap generating circuits 25, for example like the type shown in FIG. 2 are provided. Thus, if we consider capacitor C2P of FIG. 1 then a first plate of that capacitor is connected to a node 20 which represents the midpoint of a series connection between the two field effect transistors 22 and 24. The first field effect transistor 22 is the high side transistor which is operable to connect to the first plate of the capacitor C2P to Vref, whereas the second field effect transistor 24 is the low side transistor which operable to connect the first plate of the capacitor C2P to ground. Clearly if both transistors 22 and 24 are conducting at the same time then current will flow from Vref to ground and the voltage at node 20 is undefined.
In order to overcome these problems a non-overlap generator is used. An example of a prior art non-overlap generator is shown which comprises two NOR gates 26 and 27 and an inverter 28. These are connected together in the configuration shown in FIG. 2.
Suppose we start with a configuration in which each of the transistors 22 and 24 can be made conducting by sending it a “high” or “1”, and can be made non-conducting in response to a zero or “0” applied to its gate.
Starting at a steady state condition where an output 36 of the first NOR gate 26 is high, and output 42 of the second NOR gate is low and the input signal at node 30 is low, then this is a stable configuration as:    1) input 32 and 34 of NOR gate 26 are both low so output 36 remains high.    2) input 40 of NOR gate 27 is high, and the effect of the inverter 28 makes input 38 high so the output 42 remains low.
Now consider a transition, where each gate has a propagation delay D.
At switching time t=0 node 30 switches from “0” to “1”. At t=0 input 32 becomes “1” while input 34 is still zero. The output of NOR gate 26 starts to change so that it will become “0” at time t=D.
Thus as t=D input 40 of NOR gate 27 goes low. Similarly the action of the inverter causes input 38 to go low at t=D. Thus this gate starts to change state and the output 42 goes high at t=2D.
This gain represents a stable state with node 30=“1”, output 36=“0” and output 42=“1”.
It can be seen that there was a period from t=D to t=2D when both transistors were non-conducting.
Suppose now that the signal on node 30 changes from 1 to 0 at t=0.Input 32 goes low but 34 remains high so NOR gate 26 remains with its output at “0”. Meanwhile the inverter 28 is changing state such that its output becomes high. Thus at time t=D input 40 is low but input 38 is high so the NOR gate 27 starts to transition between states such that at t=2D its output is “0”. At this time the output of NOR gate 26 is also “0” but both inputs 32 and 34 have gone low so it starts to change state such that its output becomes high at t=3D.
Thus once again there was a period when both transistors 22 and 24 were non-conducting.
It is clear however that the high side and low side transistors 22 and 24 are effectively controlled in unison with one being on whilst the other is off except during a very brief window generated by the non-overlap circuit. This mode of operation is widely held by persons skilled in the art to be the way that switches for successive approximation converters are and must be driven.
For simplicity the foregoing discussion assumed that a transistor was conducting when its input was “1” and not conducting when its input was “0”. Of course this need not be the case and use of other technologies, such as CMOS, may result in the formation of the transistors who conduct when their input voltage is low. As a consequence inverters may be required to achieve the desired operation.